verilog8位数值比较器

/************
8位数值比较器
********/
module compare8(
a,   //a,b 为需要比较大8位操作数
b,
agb,//a>b
asb,//a<b
aeb //a=b
);

 

input [7:0] a,b;
output agb,asb,aeb;

 

wire [7:0] a,b;
reg agb,asb,aeb;

 

always @(a or b)
begin
    if (a>b)
     begin
          agb=1;
          asb=0;
          aeb=0;
      end
    else if (a<b)
       begin
            agb=0;
            asb=1;
            aeb=0;
        end
     
      else if(a==b)
      begin
          agb=0;
          asb=0;
          aeb=1;
      end

 

       
        else
        begin
            agb='bx;
            asb='bx;
            aeb='bx;
        end
    end
endmodule